(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of monitoring defects in a metal patterning process in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
In the manufacture of large scale integrated circuits, the metal line width or spacing is becoming smaller as technology progresses. As metal lines become thinner, micro-defects start to effect final product output (called Cp yield) and product reliability. For example, in a 0.15 μm logic process, micro metal residue has been found between metal lines. This residue is less than 0.2 μm in size. The residue, found by product failure analysis, kills product reliability. This is known as “infant mortality.” Unfortunately, this type of defect cannot be detected in-line; i.e. during fabrication; because the small size of the residue is out of the resolution limitation of defect scan tools including optical light defect inspection tools such as KLA, AIT, Compass, etc. Furthermore, the conventional Wafer Acceptance Test (WAT) spacing test key cannot catch these micro-defects. It is desired to find a way to detect micro-defects during the fabrication process.
A number of patents address testing issues. For example, U.S. Pat. No. 4,758,094 to Wihl et al shows a metal monitor for insitu qualification of reticles. U.S. Pat. No. 6,248,661B1 to Chien et al shows a method for monitoring bubble formation in a spin-on-glass process. U.S. Pat. No. 6,027,859 to Dawson et al discloses an extended test structure formed in a scribe line. U.S. Pat. No. 5,897,728 to Cole et al shows a chip attached to a temporary test structure.